module t7counter(Enable, Clock, Done);
    parameter n = 5;
    input Enable, Clock;
    output reg Done;
    
    reg [9:0] counter;
    
    initial begin
        counter = 10;
    end
    
    always @(posedge Clock) begin
        if (Enable == 1)
            counter = counter - 1;
        else
            counter = 10;
        
        if (counter == 0)
            Done = 1;
        else
            Done = 0;
    end
    
endmodule